Some semiconductor devices utilize semiconductor-on-insulator (SOI) technology, in which a thin layer of a semiconductor, such as silicon, is separated from a semiconductor substrate by a relatively thick electrically insulating layer. This thick electrically insulating layer is also referred to as a buried oxide (BOX) layer. The semiconductor layer typically has a thickness of a few nanometers, whereas the semiconductor substrate typically has a thickness of a few tens of nanometers.
SOI technology offer certain advantages compared to traditional bulk technology for Complementary Metal Oxide Semiconductor (CMOS) devices. CMOS devices include nMOSFET transistors and pMOSFET transistors both formed in the thin silicon layer which overlies the buried oxide (BOX) layer. SOI technology allows CMOS devices to operate at lower power consumption while providing the same performance level.
One particular type of SOT technology that is helping to allow for continued CMOS scaling is fully depleted SOI (FDSOI). As opposed to a partially depleted SOI (PDSOI) device, in an FDSOI device a relatively thin semiconductor channel layer is provided over the buried oxide (BOX) layer, such that the depletion region of the device covers the whole layer. FDSOI devices may provide advantages such as higher switching speeds and a reduction in threshold voltage roll off, as compared to PDSOI devices, for example.
To improve CMOS device performance, stress may be introduced into the channels of the field effect transistors (FETs). When applied in a longitudinal direction (i.e., in the direction of current flow), tensile stress is known to enhance electron mobility (i.e., n-channel MOSFET drive currents) while compressive stress is known to enhance hole mobility (i.e., p-channel MOSFET drive currents).
Consequently, tensile strained silicon-on-insulator (sSOI) is a main performance driver for nMOSFET transistors, and compressive strained silicon-germanium-on-insulator (SGOI) is a main performance driver for pMOSFET transistors.
To form an SGOI pMOSFET transistor on an sSOI substrate or wafer is difficult. Growing SiGe on an sSOI wafer often times leads to a rough surface resulting in mobility loss. In addition, a high germanium content in the silicon-germanium is needed to compensate for tensile strain. Otherwise, this leads to a high density of interface trap (DIT) value, where the DIT designates a density of traps at an interface between two layers.
One approach for forming a stressed Si/SiGe dual channel device is disclosed in U.S. published patent application no. 2013/0029478. An epitaxial SiGe layer is formed on an SOI substrate, and an Si cap layer is formed on the SiGe layer. A photoresist layer is formed on the Si cap layer, and part of the Si cap layer is removed. A Si layer is epitaxially grown on the exposed SiGe layer. An ion implantation is performed to distribute implanted ions within the silicon cap layer. Annealing is performed to relax the stress in part of the SiGe layer and transfer stress to the epitaxial Si material thereon to form strained silicon. The formed strained silicon is used to form an nMOSFET transistor channel and the region of the SiGe layer covered by photoresist is used to form a pMOSFET transistor channel.
Despite the existence of such configurations, further enhancements in SOI devices may be desirable in some applications, particularly when the SOI wafer is a stressed SOI wafer.